A 14-bit 130-MHZ cmos current-steering DAC with adjustable INL

被引：15

作者：

Chen, T ^{[1
]}

Geens, P ^{[1
]}

Van der Plas, G ^{[1
]}

Dehaene, W ^{[1
]}

Gielen, G ^{[1
]}

机构：

[1] Katholieke Univ Leuven, ESAT, MICAS, B-3001 Heverlee, Belgium

来源：

ESSCIRC 2004: PROCEEDINGS OF THE 30TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2004年

关键词：

D O I：

10.1109/ESSCIR.2004.1356644

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a 14-bit, 130-MHz CMOS current-steering DAC is presented. Different from traditional intrinsic-accuracy DACs, its INL can be improved by dynamic adjustment, which allows to reduce the chip area significantly. The layout has been carefully designed so that the signal lines of the current sources have the same length, thus good synchronization among the current sources can be achieved. The measured DNL and INL is 0.45 LSB and 0.7 LSB respectively. The SFDR is 82 dB at a 1 MHz signal frequency and 130 MHz sampling frequency. The DAC has been implemented in a standard IP5M 0.25-mum CMOS technology. The area of the current source block is 1 mm(2), and the whole core area is only 3.5 mm(2).

引用

页码：167 / 170

页数：4

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