A 14-bit 130-MHZ cmos current-steering DAC with adjustable INL

In this paper, a 14-bit, 130-MHz CMOS current-steering DAC is presented. Different from traditional intrinsic-accuracy DACs, its INL can be improved by dynamic adjustment, which allows to reduce the chip area significantly. The layout has been carefully designed so that the signal lines of the current sources have the same length, thus good synchronization among the current sources can be achieved. The measured DNL and INL is 0.45 LSB and 0.7 LSB respectively. The SFDR is 82 dB at a 1 MHz signal frequency and 130 MHz sampling frequency. The DAC has been implemented in a standard IP5M 0.25-mum CMOS technology. The area of the current source block is 1 mm(2), and the whole core area is only 3.5 mm(2).