A Power Efficient Binary Multiplier Circuit with Overflow Detection Using Single Spin Logic Circuit: Design and Implementation

被引:0
|
作者
Ghosh, Ankush [1 ]
Sarkar, Souvik [2 ]
Chaudhuri, D. Ray [3 ]
Sarkar, Subir Kumar [1 ]
机构
[1] Jadavpur Univ, Dept Elect & Telecommun Engn, Kolkata 700032, India
[2] Govt Coll Engn & Ceram Technol, Dept CSE, Kolkata 700015, India
[3] Univ Calcutta, Dept Elect Sci, Kolkata 700009, W Bengal, India
关键词
D O I
10.1166/asl.2009.1071
中图分类号
O [数理科学和化学]; P [天文学、地球科学]; Q [生物科学]; N [自然科学总论];
学科分类号
07 ; 0710 ; 09 ;
摘要
The basic needs of modern Electronic industry are low power consumption high operating speed and high integration density equipments. As a consequence, the search for new principle of operation of the small size and low power consuming devices is becoming more and more important. Recent advances in controlling quantum 'spin' effect have broaden the path for the newly emerging field, called 'spin based electronic' or 'spintronics.' It is not the electronic charge but the electrons spin that carry information and they offer opportunities for a new generation of novel devices that are extremely fast. In spin based electronics information is injected, stored or manipulated with spin degree of freedom. In the present work, several multipliers (with overflow detection capability) like unsigned array multipliers, unsigned tree multipliers and two's complement multipliers are realized employing single spin logic circuit to save area and time.
引用
收藏
页码:391 / 397
页数:7
相关论文
共 50 条
  • [11] Efficient logic circuit for network intrusion detection
    Roan, Huang-Chun
    Ou, Chien-Min
    Hwang, Wen-Jyi
    Lo, Chia-Tien Dan
    EMBEDDED AND UBIQUITOUS COMPUTING, PROCEEDINGS, 2006, 4096 : 776 - 784
  • [12] Design of energy efficient domino logic circuit using lector technique
    Verma, Km Anjali
    Kumar, Manish
    Kumar, Saurabh
    Chauhan, R. K.
    INTERNATIONAL JOURNAL OF ELECTRONICS, 2023, 110 (11) : 2117 - 2135
  • [13] Ultra low power design of multi-valued logic circuit for binary interfaces
    Jhamb, Mansi
    Mohan, Ratnesh
    JOURNAL OF KING SAUD UNIVERSITY-COMPUTER AND INFORMATION SCIENCES, 2022, 34 (08) : 5578 - 5586
  • [14] Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation
    Thamizharasan, V.
    Parthipan, V.
    SCIENTIFIC REPORTS, 2024, 14 (01)
  • [15] FPGA Implementation of Threshold-Type Binary Memristor and Its Application in Logic Circuit Design
    Yang, Liu
    Wang, Yuqi
    Wu, Zhiru
    Wang, Xiaoyuan
    MICROMACHINES, 2021, 12 (11)
  • [16] Effect of FPGA Circuit Implementation on Error Detection Using Logic Implication Checking
    Afzaal, Umar
    Hassan, Abdus Sami
    Arifeen, Tooba
    Lee, Jeong-A
    2018 21ST EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2018), 2018, : 196 - 200
  • [17] Design a chaotic circuit using tunable and power efficient memristor emulator circuit for image encryption
    Kumari, Usha
    Yadav, Rekha
    PHYSICA SCRIPTA, 2025, 100 (01)
  • [18] Implementation of energy efficient circuit design using A* algorithm in embedded network
    Anil, G. L.
    Iqbal, J. L. Mazher
    MICROPROCESSORS AND MICROSYSTEMS, 2020, 74
  • [19] Logic Synthesis of Binarized Neural Networks for Efficient Circuit Implementation
    Chi, Chia-Chih
    Jiang, Jie-Hong R.
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 41 (04) : 993 - 1005
  • [20] Logic Synthesis of Binarized Neural Networks for Efficient Circuit Implementation
    Chi, Chia-Chih
    Jiang, Jie-Hong R.
    2018 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) DIGEST OF TECHNICAL PAPERS, 2018,