A Power Efficient Binary Multiplier Circuit with Overflow Detection Using Single Spin Logic Circuit: Design and Implementation

被引:0
|
作者
Ghosh, Ankush [1 ]
Sarkar, Souvik [2 ]
Chaudhuri, D. Ray [3 ]
Sarkar, Subir Kumar [1 ]
机构
[1] Jadavpur Univ, Dept Elect & Telecommun Engn, Kolkata 700032, India
[2] Govt Coll Engn & Ceram Technol, Dept CSE, Kolkata 700015, India
[3] Univ Calcutta, Dept Elect Sci, Kolkata 700009, W Bengal, India
关键词
D O I
10.1166/asl.2009.1071
中图分类号
O [数理科学和化学]; P [天文学、地球科学]; Q [生物科学]; N [自然科学总论];
学科分类号
07 ; 0710 ; 09 ;
摘要
The basic needs of modern Electronic industry are low power consumption high operating speed and high integration density equipments. As a consequence, the search for new principle of operation of the small size and low power consuming devices is becoming more and more important. Recent advances in controlling quantum 'spin' effect have broaden the path for the newly emerging field, called 'spin based electronic' or 'spintronics.' It is not the electronic charge but the electrons spin that carry information and they offer opportunities for a new generation of novel devices that are extremely fast. In spin based electronics information is injected, stored or manipulated with spin degree of freedom. In the present work, several multipliers (with overflow detection capability) like unsigned array multipliers, unsigned tree multipliers and two's complement multipliers are realized employing single spin logic circuit to save area and time.
引用
收藏
页码:391 / 397
页数:7
相关论文
共 50 条
  • [21] A CMOS adiabatic logic for low power circuit design
    Song, HS
    Kang, JK
    PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 2004, : 348 - 351
  • [22] Design of a Multiplier with Adaptive Hold Logic (AHL) circuit to reduce Aging Effects
    Chirde, Vaishali S.
    Jadhav, Usha
    2015 INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION AND SECURITY (ICCCS), 2015,
  • [23] Design of a Multiplier with Adaptive Hold Logic (AHL) circuit to reduce Aging Effects
    Chirde, Vaishali S.
    Jadhav, Usha
    2015 INTERNATIONAL CONFERENCE ON COMPUTER, COMMUNICATION AND CONTROL (IC4), 2015,
  • [24] Combinational circuit design using Nanomagnetic logic
    Feena, J. Jelin
    Manickavasagam, S.
    2014 INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES), 2014,
  • [25] A Design of PUF Circuit Using Adiabatic Logic
    Nagata, Shoya
    Takahashi, Yasuhiro
    2024 IEEE THE 20TH ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, APCCAS 2024, 2024, : 595 - 598
  • [26] Sequential Circuit Design with Bilayer Avalanche Spin Diode Logic
    Vyas, Vaibhav
    Friedman, Joseph S.
    NANOARCH'18: PROCEEDINGS OF THE 14TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES, 2018, : 49 - 50
  • [27] Compact Modeling for Power Efficient Circuit Design
    Miura-Mattausch, M.
    Kikuchihara, H.
    Kajiwara, T.
    Tanimoto, Y.
    Saito, A.
    Iizuka, T.
    Navarro, D.
    Mattausch, H. J.
    2018 48TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC), 2018, : 234 - 237
  • [28] Design and implementation of XOR logic circuit based on generalized memristor
    Jiang, Fenghu
    Yuan, Fang
    Li, Yuxia
    EUROPEAN PHYSICAL JOURNAL-SPECIAL TOPICS, 2022, 231 (03): : 481 - 491
  • [29] Design and Simulation of Low Power Dynamic Logic Circuit Using Footed Diode Domino Logic
    Kumar, Sujeet
    Singhal, Sanchit
    Pandey, Amit Kumar
    Nagaria, R. K.
    2013 STUDENTS CONFERENCE ON ENGINEERING AND SYSTEMS (SCES): INSPIRING ENGINEERING AND SYSTEMS FOR SUSTAINABLE DEVELOPMENT, 2013,
  • [30] VLSI design and implementation of an improved squaring circuit by combinational logic
    Abdel-Aty-Zohdy, HS
    Hiasat, AA
    THIRTY-FIRST ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, VOLS 1 AND 2, 1998, : 426 - 429