A Power Efficient Binary Multiplier Circuit with Overflow Detection Using Single Spin Logic Circuit: Design and Implementation

被引:0
|
作者
Ghosh, Ankush [1 ]
Sarkar, Souvik [2 ]
Chaudhuri, D. Ray [3 ]
Sarkar, Subir Kumar [1 ]
机构
[1] Jadavpur Univ, Dept Elect & Telecommun Engn, Kolkata 700032, India
[2] Govt Coll Engn & Ceram Technol, Dept CSE, Kolkata 700015, India
[3] Univ Calcutta, Dept Elect Sci, Kolkata 700009, W Bengal, India
关键词
D O I
10.1166/asl.2009.1071
中图分类号
O [数理科学和化学]; P [天文学、地球科学]; Q [生物科学]; N [自然科学总论];
学科分类号
07 ; 0710 ; 09 ;
摘要
The basic needs of modern Electronic industry are low power consumption high operating speed and high integration density equipments. As a consequence, the search for new principle of operation of the small size and low power consuming devices is becoming more and more important. Recent advances in controlling quantum 'spin' effect have broaden the path for the newly emerging field, called 'spin based electronic' or 'spintronics.' It is not the electronic charge but the electrons spin that carry information and they offer opportunities for a new generation of novel devices that are extremely fast. In spin based electronics information is injected, stored or manipulated with spin degree of freedom. In the present work, several multipliers (with overflow detection capability) like unsigned array multipliers, unsigned tree multipliers and two's complement multipliers are realized employing single spin logic circuit to save area and time.
引用
收藏
页码:391 / 397
页数:7
相关论文
共 50 条
  • [31] Design of Energy Efficient Voltage Multiplier Circuit for RF Energy Harvesting
    Rajawat, Asmita
    Singhal, P. K.
    ADVANCES IN SMART GRID AND RENEWABLE ENERGY, 2018, 435 : 583 - 592
  • [32] Design and implementation of XOR logic circuit based on generalized memristor
    Fenghu Jiang
    Fang Yuan
    Yuxia Li
    The European Physical Journal Special Topics, 2022, 231 : 481 - 491
  • [33] Low power dynamic logic circuit design using a pseudo dynamic buffer
    Tang, Fang
    Bermak, Amine
    Gu, Zhouye
    INTEGRATION-THE VLSI JOURNAL, 2012, 45 (04) : 395 - 404
  • [34] Design of Binary Convolution Operation Circuit for Binarized Neural Networks Using Single-Flux-Quantum Circuit
    Li, Zongyuan
    Yamanashi, Yuki
    Yoshikawa, Nobuyuki
    IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2022, 32 (04)
  • [35] Non-Binary Spin Wave Based Circuit Design
    Mahmoud, Abdulqader Nael
    Vanderveken, Frederic
    Ciubotaru, Florin
    Adelmann, Christoph
    Hamdioui, Said
    Cotofana, Sorin
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2022, 69 (10) : 3888 - 3900
  • [36] Implementation of an Efficient Library for Asynchronous Circuit Design with Synopsys
    Caohuu, Tri
    Edwards, John
    PROGRESS IN SYSTEMS ENGINEERING, 2015, 366 : 465 - 471
  • [37] Design of a low-power 8 x 8-bit parallel multiplier using MOS current mode logic circuit
    Kim, J. B.
    Lee, Y. S.
    INTERNATIONAL JOURNAL OF ELECTRONICS, 2007, 94 (10) : 905 - 913
  • [38] All Optical Design of Cost Efficient Multiplier Circuit Using Terahertz Optical Asymmetric Demultiplexer
    Manna, Arpan
    Saha, Subham
    Das, Rakesh
    Bandyopadhyay, Chandan
    Rahaman, Hafizur
    2017 7TH INTERNATIONAL SYMPOSIUM ON EMBEDDED COMPUTING AND SYSTEM DESIGN (ISED), 2017,
  • [39] An efficient low power method for FinFET domino OR logic circuit
    Kajal
    Sharma, Vijay Kumar
    MICROPROCESSORS AND MICROSYSTEMS, 2022, 95
  • [40] Power Efficient LCR Dual Keeper Domino Logic Circuit
    Deo, Manish
    Kumar, Manish
    JOURNAL OF ACTIVE AND PASSIVE ELECTRONIC DEVICES, 2021, 16 (01): : 61 - 69