Flip-Flop Upsets From Single-Event-Transients in 65 nm Clock Circuits

被引:12
|
作者
Wissel, Larry [1 ]
Heidel, David F. [2 ]
Gordon, Michael S. [2 ]
Rodbell, Kenneth P. [2 ]
Stawiasz, Kevin [2 ]
Cannon, Ethan H. [1 ]
机构
[1] IBM Corp, Syst & Technol Grp, Essex Jct, VT 05452 USA
[2] IBM Corp, TJ Watson Res Lab, Yorktown Hts, NY 10598 USA
关键词
Flip-flop; single-event transient; soft error;
D O I
10.1109/TNS.2009.2033997
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper describes upsets of 65 nm flip-flops caused by Single-Event-Transients in clock-tree circuits. The upset rate is predicted through modeling, and compared to upset rates measured on a 65 nm test chip with 15 MeV carbon ions and 148 MeV protons.
引用
收藏
页码:3145 / 3151
页数:7
相关论文
共 50 条
  • [21] A new single-clock flip-flop for half-swing clocking
    Kwon, YS
    Park, IC
    Kyung, CM
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1999, E82A (11) : 2521 - 2526
  • [22] Application of clock gating techniques at a flip-flop level to switching noise reduction in VLSI circuits
    Parra, P
    Castro, J
    Valencia, M
    Acosta, AJ
    VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2, 2005, 5837 : 1003 - 1014
  • [23] Timing Analysis of Dual-Edge-Triggered Flip-Flop Based Circuits with Clock Gating
    Oh, Chungki
    Kim, Sangmin
    Shin, Youngsoo
    2009 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS, 2009, : 59 - 62
  • [24] Single-Event-Upset Tolerant RS Flip-Flop with Small Area
    Namba, Kazuteru
    Nakashima, Kengo
    Ito, Hideo
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2010, E93D (12) : 3407 - 3409
  • [25] A single event upset hardened flip-flop design utilizing layout technique
    Wang, Haibin
    Chu, Jiamin
    Wei, Jinghe
    Shi, Junwei
    Sun, Hongwen
    Han, Jianwei
    Qian, Rong
    MICROELECTRONICS RELIABILITY, 2019, 102
  • [26] Single-Event Performance of Differential Flip-Flop Designs and Hardening Implication
    Chen, R. M.
    Zhang, E. X.
    Bhuva, B. L.
    2016 IEEE 22ND INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS), 2016, : 221 - 226
  • [27] A Radiation-Hardened Non-redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process
    Yamaguchi, Junki
    Furuta, Jun
    Kobayashi, Kazutoshi
    2015 15TH EUROPEAN CONFERENCE ON RADIATION AND ITS EFFECTS ON COMPONENTS AND SYSTEMS (RADECS), 2015,
  • [28] A Radiation-Hardened Non-Redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process
    Furuta, Jun
    Yamaguchi, Junki
    Kobayashi, Kazutoshi
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2016, 63 (04) : 2080 - 2086
  • [29] Clock, Flip-Flop, and Combinatorial Logic Contributions to the SEU Cross Section in 90 nm ASIC Technology
    Hansen, David L.
    Miller, Eric J.
    Kleinosowski, Aj
    Kohnen, Kirk
    Le, Anthony
    Wong, Dick
    Amador, Karina
    Baze, Mark
    DeSalvo, David
    Dooley, Maryanne
    Gerst, Kenneth
    Hughlock, Barrie
    Jeppson, Bradford
    Jobe, R. D.
    Nardi, David
    Ojalvo, Isabel
    Rasmussen, Brad
    Sunderland, David
    Truong, John
    Yoo, Michael
    Zayas, E.
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2009, 56 (06) : 3542 - 3550
  • [30] Single event upset reinforcement technology of DICE flip-flop based on layout design
    Lai, Xiaoling
    Zhang, Jian
    Ju, Ting
    Zhu, Qi
    Guo, Yangming
    Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University, 2022, 40 (06): : 1305 - 1311