Test Planning and Test Access Mechanism Design for Stacked Chips using ILP

被引：0

作者：

SenGupta, Breeta ^{[1
]}

Larsson, Erik ^{[1
]}

机构：

[1] Lund Univ, Lund, Sweden

来源：

2014 IEEE 32ND VLSI TEST SYMPOSIUM (VTS) | 2014年

关键词：

OPTIMIZATION;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we propose a scheme for test planning and test access mechanism (TAM) design for stacked integrated circuits (SICs) that are designed in a core-based manner. Our scheme minimizes the test cost, which is given as the weighted sum of the test time and the TAM width. The test cost is evaluated for a test flow that consists of a wafer sort test of each individual chip and a package test of the complete stack of chips. We use an Integer Linear Programming (ILP) model to find the optimal test cost. The ILP model is implemented on several designs constructed from ITC'02 benchmarks. The experimental results show significant reduction in test cost compared to when using schemes, which are optimized for non-stacked chips.

引用

页数：6

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