IBM POWER9 PROCESSOR ARCHITECTURE

被引：70
|
作者：
Sadasivam, Satish Kumar [1 ]
Thompto, Brian W. [2 ]
Kalla, Ron [3 ]
Starke, William J. [1 ]
机构：
[1] IBM Corp, Armonk, NY 10504 USA
[2] IBM Corp, Power Syst Processor Team, Armonk, NY 10504 USA
[3] IBM Corp, Power9, Armonk, NY 10504 USA
来源：
IEEE MICRO | 2017年 / 37卷 / 02期
关键词：
accelerator; cache; CAPI; field-programmable gate array; FPGA; GPU; I/O; interconnects; memory; microarchitecture; multicore; POWER9; processor; simultaneous multithreading; SMP; SMT; symmetric multiprocessor;
D O I：
10.1109/MM.2017.40
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
THE IBM POWER9 PROCESSOR HAS AN ENHANCED CORE AND CHIP ARCHITECTURE OPTIMIZED FOR EMERGING WORKLOADS WITH SUPERIOR THREAD PERFORMANCE AND HIGHER THROUGHPUT TO SUPPORT NEXT-GENERATION COMPUTING. MULTIPLE VARIANTS OF SILICON TARGET THE SCALE-OUT AND SCALE-UP MARKETS. WITH A NEW CORE MICROARCHITECTURE DESIGN, ALONG WITH AN INNOVATIVE I/O FABRIC TO SUPPORT ACCELERATED COMPUTING REQUIREMENTS, THE POWER9 PROCESSOR MEETS THE DIVERSE COMPUTING NEEDS OF THE COGNITIVE ERA AND PROVIDES A PLATFORM FOR ACCELERATED COMPUTING.
引用
收藏
页码：40 / 51
页数：12
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