Architecture and performance of the hardware accelerators in IBM's PowerEN processor

被引：0
|
作者：
Heil, Timothy [1 ,2 ]
Krishna, Anil [1 ,3 ]
Lindberg, Nicholas [1 ,4 ]
Toussi, Farnaz [1 ,5 ]
Vanderwiel, Steven [1 ,5 ]
机构：
[1] International Business Machines Corp., United States
[2] Microsoft Research, Seattle,WA, United States
[3] CPU R and D, Qualcomm, Raleigh,NC, United States
[4] Milwaukee Institute, Milwaukee,WI, United States
[5] System and Technology Group, IBM, Rochester,MN, United States
来源：
ACM Transactions on Parallel Computing | 2014年 / 1卷 / 01期
关键词：
XML;
D O I：
10.1145/2588888
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 50 条
  • [1] Hardware Acceleration in the IBM PowerEN Processor: Architecture and Performance
    Krishna, Anil
    Heil, Timothy
    Lindberg, Nicholas
    Toussi, Farnaz
    VanderWiel, Steven
    PROCEEDINGS OF THE 21ST INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES (PACT'12), 2012, : 389 - 399
  • [2] Hardware-Accelerated Regular Expression Matching with Overlap Handling on IBM PowerEN™ Processor
    Atasu, Kubilay
    Doerfler, Florian
    van Lunteren, Jan
    Hagleitner, Christoph
    IEEE 27TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM (IPDPS 2013), 2013, : 1254 - 1265
  • [3] Architectural Perspectives of Future Wireless Base Stations based on the IBM PowerEN™ Processor
    Vega, Augusto
    Bose, Pradip
    Buyuktosunoglu, Alper
    Derby, Jeff
    Franceschini, Michele
    Johnson, Charles
    Montoye, Robert
    2012 IEEE 18TH INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA), 2012, : 423 - 432
  • [4] IBM PowerNP network processor: Hardware, software, and applications
    Allen, JR
    Bass, BM
    Basso, C
    Boivie, RH
    Calvignac, JL
    Davis, GT
    Frelechoux, L
    Heddes, M
    Herkersdorf, A
    Kind, A
    Logan, JF
    Peyravian, M
    Rinaldi, MA
    Sabhikhi, RK
    Siegel, MS
    Waldvogel, M
    IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2003, 47 (2-3) : 177 - 193
  • [5] Performance Interfaces for Hardware Accelerators
    Ma, Jiacheng
    Iyer, Rishabh
    Kashani, Sahand
    Emami, Mahyar
    Bourgeat, Thomas
    Candea, George
    PROCEEDINGS OF THE 18TH USENIX SYMPOSIUM ON OPERATING SYSTEMS DESIGN AND IMPLEMENTATION, OSDI 2024, 2024, : 855 - 874
  • [6] IBM POWER9 PROCESSOR ARCHITECTURE
    Sadasivam, Satish Kumar
    Thompto, Brian W.
    Kalla, Ron
    Starke, William J.
    IEEE MICRO, 2017, 37 (02) : 40 - 51
  • [7] THE IBM RISC SYSTEM-6000 PROCESSOR - HARDWARE OVERVIEW
    BAKOGLU, HB
    GROHOSKI, GF
    MONTOYE, RK
    IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1990, 34 (01) : 12 - 22
  • [8] Software and Hardware Design Issues for Low Complexity High Performance Processor Architecture
    Masuda, Masashi
    Ben Abdallah, Abderazek
    Canedo, Arquimedes
    2009 INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING WORKSHOPS (ICPPW 2009), 2009, : 558 - +
  • [9] APNAS: Accuracy-and-Performance-Aware Neural Architecture Search for Neural Hardware Accelerators
    Achararit, Paniti
    Hanif, Muhammad Abdullah
    Putra, Rachmad Vidya Wicaksana
    Shafique, Muhammad
    Hara-Azumi, Yuko
    IEEE ACCESS, 2020, 8 : 165319 - 165334
  • [10] The Case for Performance Interfaces for Hardware Accelerators
    Iyer, Rishabh
    Ma, Jiacheng
    Argyraki, Katerina
    Candea, George
    Ratnasamy, Sylvia
    PROCEEDINGS OF THE 19TH WORKSHOP ON HOT TOPICS IN OPERATING SYSTEMS, HOTOS 2023, 2023, : 38 - 45
12345