Doping fluctuation effects in multiple-gate SOI MOSFETs

被引:1
|
作者
Colinge, C. A. [1 ]
Xiong, W. [2 ]
Cleavelin, C. R. [2 ]
Colinge, J. -P. [3 ]
机构
[1] Texas Instruments Inc, SiTD, Dallas, TX 75265 USA
[2] Infineon Technolo, D-85579 Neubiberg, Germany
[3] Univ Calif Davis, Dept Elect & Comp Engn, Davis, CA 95616 USA
关键词
silicon-on-insulator; doping fluctuations; SOI MOSFET; multiple-gate; MOSFETs;
D O I
10.1007/978-1-4020-6380-0_12
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Random doping fluctuation effects are studied in multiple-gate SOI MOSFETs (MuGFETs) using numerical simulation. The presence of a single doping impurity atom increases threshold voltage. Electrical parameters vary with the physical location of the impurity atom.
引用
收藏
页码:165 / +
页数:2
相关论文
共 50 条
  • [31] Transformation of hydrogen silsesquioxane properties with RIE plasma treatment for advanced multiple-gate MOSFETs
    Penaud, J.
    Fruleux, F.
    Dubois, E.
    APPLIED SURFACE SCIENCE, 2006, 253 (01) : 395 - 399
  • [32] A Unified Quasi-3D Subthreshold Behavior Model for Multiple-Gate MOSFETs
    Liou, Juin J.
    Gao, Hong-Wun
    Wang, Yeong-Her
    Chiang, Te-Kuang
    IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2018, 17 (04) : 763 - 771
  • [33] Effects of gate structures on the RF performance in PD SOI MOSFETs
    Lee, BJ
    Kim, K
    Yu, CG
    Lee, JH
    Park, JT
    IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, 2005, 15 (04) : 223 - 225
  • [34] Multiple - Gate Silicon on Insulator (SOI) MOSFETs: Device Design and Analysis
    Dayal, Aditya
    Pandey, Satya Prakash
    Khandelwal, Saurabh
    Akashe, Shyam
    2013 ANNUAL INTERNATIONAL CONFERENCE ON EMERGING RESEARCH AREAS & 2013 INTERNATIONAL CONFERENCE ON MICROELECTRONICS, COMMUNICATIONS & RENEWABLE ENERGY (AICERA/ICMICR), 2013,
  • [35] Study of the corner effects on pi-gate SOI MOSFETs
    Ruiz, F. G.
    Godoy, A.
    Gamiz, F.
    Donetti, L.
    Sampedro, C.
    2007 SPANISH CONFERENCE ON ELECTRON DEVICES, PROCEEDINGS, 2007, : 76 - +
  • [36] Multi-gate SOI MOSFETs
    Colinge, J. P.
    MICROELECTRONIC ENGINEERING, 2007, 84 (9-10) : 2071 - 2076
  • [37] Fin thickness asymmetry effects in multiple-gate SOIFETs (MuGFETs)
    Schulz, T
    Xiong, W
    Cleavelin, CR
    Schruefer, K
    Gostkowski, M
    Matthews, K
    Gebara, G
    Zaman, RJ
    Patruno, P
    Chaudhry, A
    Woo, A
    Colinge, JP
    2005 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2005, : 154 - 156
  • [38] Discrete Dopant Induced Characteristic Fluctuations in 16nm Multiple-Gate SOI Devices
    Li, Yiming
    Hwang, Chih-Hong
    Huang, Hsuan-Ming
    Yeh, Ta-Ching
    2007 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS, 2007, : 117 - 118
  • [39] Junctionless Multiple-Gate (JLMG) MOSFETs: A Unified Subthreshold Current Model to Assess Noise Margin of Subthreshold Logic Gate
    Chiang, Te-Kuang
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2021, 68 (10) : 5330 - 5334
  • [40] Reduction in threshold voltage fluctuation in fully-depleted SOI MOSFETs with back gate control
    Numata, T
    Noguchi, M
    Takagi, S
    SOLID-STATE ELECTRONICS, 2004, 48 (06) : 979 - 984