Reduction in threshold voltage fluctuation in fully-depleted SOI MOSFETs with back gate control

被引:6
|
作者
Numata, T
Noguchi, M
Takagi, S
机构
[1] Toshiba Co Ltd, Adv LSI Technol Lab, Isogo Ku, Yokohama, Kanagawa 2358522, Japan
[2] Toshiba Co Ltd, Semicond Co, Yokohama, Kanagawa 2358522, Japan
关键词
MOSFETs; silicon-on-insulator; threshold voltage;
D O I
10.1016/j.sse.2003.12.018
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents the effects of the back gate control on the threshold voltage fluctuation in fully-depleted SOI MOSFETs. Particularly, we mainly examine the threshold voltage fluctuation due to the variations of the SOI thickness. It is found that the absence of threshold voltage fluctuation due to the SOI thickness variation can be achieved by appropriately choosing given values of back gate voltage and channel impurity concentration. This is because the back gate bias and the channel impurity concentration have SOI thickness dependence opposite to that of the threshold voltage. On the other hand, short channel effects are another factor affecting the threshold voltage fluctuation due to the SOI thickness variation in the case of short gate length. It is shown that application of the back gate bias is a better way to suppress short channel effects than the increase in the channel doping under a constant value of threshold voltage. It is found that the suppression of the threshold voltage fluctuation by applying the back gate bias is still maintained down to gate length of 50 nm. (C) 2004 Elsevier Ltd. All rights reserved.
引用
收藏
页码:979 / 984
页数:6
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