Doping fluctuation effects in multiple-gate SOI MOSFETs

被引：1

作者：

Colinge, C. A. ^{[1
]}

Xiong, W. ^{[2
]}

Cleavelin, C. R. ^{[2
]}

Colinge, J. -P. ^{[3
]}

机构：

[1] Texas Instruments Inc, SiTD, Dallas, TX 75265 USA

[2] Infineon Technolo, D-85579 Neubiberg, Germany

[3] Univ Calif Davis, Dept Elect & Comp Engn, Davis, CA 95616 USA

来源：

NANOSCALED SEMICONDUCTOR-ON-INSULATOR STRUCTURES AND DEVICES | 2007年

关键词：

silicon-on-insulator; doping fluctuations; SOI MOSFET; multiple-gate; MOSFETs;

D O I：

10.1007/978-1-4020-6380-0_12

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Random doping fluctuation effects are studied in multiple-gate SOI MOSFETs (MuGFETs) using numerical simulation. The presence of a single doping impurity atom increases threshold voltage. Electrical parameters vary with the physical location of the impurity atom.

引用

页码：165 / +

页数：2

共 50 条

[41] Intra-Cell Process Variability and Compact Modeling of LWR Effects: from Self-Aligned Multiple Patterning to Multiple-Gate MOSFETs
Chen, Yijian
Kang, Weiling
Cheng, Qi
DESIGN FOR MANUFACTURABILITY THROUGH DESIGN-PROCESS INTEGRATION VI, 2012, 8327
[42] Total dose effects on double gate fully depleted SOI MOSFETs
Jun, BG
Xiong, HD
Sternberg, AL
Cirba, CR
Chen, DK
Schrimpf, RD
Fleetwood, DM
Schwank, JR
Cristoloveanu, S
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2004, 51 (06) : 3767 - 3772
[43] Study of thermal effects on thin double gate SOI MOSFETs characteristics
Gharabagi, R
2004 IEEE REGION 5 CONFERENCE: ANNUAL TECHNICAL AND LEADERSHIP WORKSHOP, 2004, : 107 - 111
[44] Experimental gate misalignment analysis on double gate SOI MOSFETs
Widiez, J
Daugé, F
Vinet, M
Poiroux, T
Previtali, B
Mouis, M
Deleonibus, S
2004 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2004, : 185 - 186
[45] Role of the gate in ballistic nanowire SOI MOSFETs
Mangla, A.
Sallese, J. -M.
Sampedro, C.
Gamiz, F.
Enz, C.
SOLID-STATE ELECTRONICS, 2015, 112 : 24 - 28
[46] MEASUREMENT OF INTRINSIC GATE CAPACITANCES OF SOI MOSFETS
FLANDRE, D
VANDEWIELE, F
JESPERS, PGA
HAOND, M
IEEE ELECTRON DEVICE LETTERS, 1990, 11 (07) : 291 - 293
[47] PUNCHTHROUGH PATH IN DOUBLE GATE SOI MOSFETS
NIU, GF
RUAN, G
SOLID-STATE ELECTRONICS, 1995, 38 (10) : 1848 - 1850
[48] PROBLEMS IN MULTIPLE-GATE ISFETS FOR INVIVO USE
JORDAN, WS
BUSSEY, B
WESTENSKOW, DR
JANATA, J
IEEE TRANSACTIONS ON BIOMEDICAL ENGINEERING, 1984, 31 (08) : 582 - 582
[49] Back gate effects on threshold voltage sensitivity to SOI thickness in fully-depleted SOI MOSFETs
Noguchi, M
Numata, T
Mitani, Y
Shino, T
Kawanaka, S
Oowaki, Y
Toriumi, A
IEEE ELECTRON DEVICE LETTERS, 2001, 22 (01) : 32 - 34
[50] A multiple-gate runner system for gravity casting
Hsu, Fu-Yuan
Jolly, Mark R.
Campbell, John
JOURNAL OF MATERIALS PROCESSING TECHNOLOGY, 2009, 209 (17) : 5736 - 5750

← 1 2 3 4 5 →