System-level metrics for hardware/software architectural mapping

被引：0

作者：

Ferrandi, F ^{[1
]}

Lanzi, P ^{[1
]}

Sciuto, D ^{[1
]}

Tanelli, M ^{[1
]}

机构：

[1] Politecn Milan, Dip Electtron & Informaz, I-20133 Milan, Italy

来源：

DELTA 2004: SECOND IEEE INTERNATIONAL WORKSHOP ON ELECTRONIC DESIGN, TEST APPLICATIONS, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The current trend in Embedded Systems (ES) design is moving towards the integration of increasingly complex applications on a single chip, while having to meet strict market demands which force to face always shortening design times. In general, the ideal design methodology shall support the exploration of the highest possible number of alternatives (in terms of HW-SW architectures) starting in the early design stages as this will prevent costly correction efforts in the deployment phase. The present paper will propose a new methodology for tackling the design exploration problem, with the aim of providing a solution in terms of optimal partitioning with respect of the overall system performance.

引用

页码：231 / 236

页数：6

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