50-nm MOSFET with electrically induced source/drain extensions

A new bulk 50-nm MOSFET with n(+) poly-Si side gates has been proposed and fabricated by using a mix-and-match technique. A main gate with a work function different from that of n(+) poly-Si side gates is adopted. In this work, p(+) poly-Si is used for the main gate. Due to n(+) floating side gates (FSG) at both sides of the main gate, inversion layer is induced under the FSG and acts as an extended source/drain (S/D). Using 50-nm E-beam lithography and electron cyclotron resonance N2O radical oxidation for the inter-gate oxide, a 50-nm NMOSFET was fabricated successfully, From the I-V characteristics, we obtained I-on = 690 muA/mum at V-GS-V-TH = V-DS = 1.5 V for an intrinsic 50-nm NMOSFET with a 3-nm gate oxide. We investigated the effect of the FSGs on the device characteristics and verified their reasonable operation. The coupling ratio of the main gate to the FSG of the device was about 0.75. We found that the device had excellent short-channel threshold-voltage (V-TH) roll-off characteristics due to ail ultra shallow induced extended S/D.