Source/Drain Engineering for High Performance Vertical MOSFET

In this paper, Source,Drain (S/D) engineering for high performance (HP) Vertical MOSFET (V-MOSFET) in 3Xnm generation and its beyond is investigated, by using gradual S/D profile while degradation of driving current (I-ON) due to the parasitic series resistance (R-para) is minimized through two-dimensional device simulation taking into account for gate-induced-drain-leakage (GIDL). In general, it is significant to reduce spreading resistance in the case of conventional Planar MOSFET. Therefore, in this study, we focused and analyzed the abruptness of diffusion layer that is still importance parameter in V-MOSFET. First, for improving the basic device performance such as subthreshold swing (SS), I-ON, and R-para, S/D engineering is investigated. The dependency of device performance on S/D abruptness (sigma(S/D)) for various Lightly Doped Drain Extension (LDD) abruptness (sigma(LDD)) is analyzed. In this study, Spacer Length (L-SP) is defined as a function of sigma(S/D). As sigma(S/D) becomes smaller and S/D becomes more abrupt, L-SP becomes shorter. SS depends on the sigma(S/D) rather than the sigma(LDD). I-ON has the peak value of I 750 mu A/mu m at sigma(S/D) = 2 nm/dec. and sigma(LDD)=3 nm/dec. when the silicon pillar diameter (D) is 30 nm and the gate length (Lg) is 60nm. As sigma(S/D) becomes small, higher I-ON is obtained due to reduction of R-para while SS is degraded. However, when sigma(S/D) becomes too small in the short channel devices (Lg = 60 nm and Lg = 45 nm), I-ON is degraded because the leakage current clue to GIDL is increased and reaches I-OFF limit of 100 nA/mu m. In addition, as sigma(LDD) becomes larger, larger I-ON is obtained in the case of Lg = 100 nm and Lg = 60 nm because channel length becomes shorter. On the other hand, in the case of Lg = 45 nm, as sigma(LDD) becomes larger, I-ON is degraded because short channel effect (SCE) becomes significant. Next, the dependency of the basic device performance on D is investigated. By slimming D from 30 nm to 10 nm, while SS is improved and approaches the ideal value of 60 mV/Decade, I-ON is degraded clue to increase of on-resistance (R-on). From these results, it is necessary to reduce R-para while I-OFF meets limit of 100 nA/mu m for designing S/D of HP V-MOSFET. Especially for the V-MOSFET in the IXnm generation and its beyond, the influence of the and R-para GIDL on I-ON becomes more significant, and therefore, the trade-off between sigma(S/D) and I-ON has a much greater impact on S/D engineering of V-MOSFET.