Gate-to-source/drain Fringing Capacitance Model with Process Variation of MOSFET in 40nm Generation

In this paper, a semi-analytical model for the gate-to-source/drain fringing capacitance (C-f) of MOSFET including process variations is presented. C-f is defined as a layout-dependent parasitic capacitance separated from gate-to-contact capacitance (C-co), and is composed of several dual-k perpendicular-plate capacitances. Layout-dependent coefficients such as gate to contact space (CPS) and contact to contact space (CCS) are found to significantly influence C-f. According to the silicon data, C-f model is optimized including the process variation. The errors between silicon data and simulation are under 15%. The proposed model can improve the precision for digital and RF circuit simulation in sub-nanometer technology generation.