A comparison of bit-serial and multi-bit processor elements in a real-time signal processing SIMD architecture

被引:0
|
作者
Astrom, A
Hall, M
Edman, A
机构
关键词
D O I
10.1109/HIPC.1996.565830
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Today, it is accepted to say that the more bits you have got in your micro processor, the better performance you will have. This is probably true if only the performance is concerned. However, if the chip size of the processor is taken into account this might not be the case. In massively parallel architecture, chip area is an important figure. This is especially true for air-borne and, to certain extend industrial real-time applications. In this paper we study the impact of multi bit processors on the linear SIMD array called RVIP which is an architecture used for real-time radar signal processing. In RVIP, each processing element is bit serial. The results show that the gain in using multi bit processors is very little and that the optimal bit number probably is one or two. We believe that the results from this study can be transferred to other similar systems.
引用
收藏
页码:245 / 250
页数:6
相关论文
共 50 条
  • [1] A BIT-SERIAL VLSI ARCHITECTURE FOR GENERATING MOMENTS IN REAL-TIME
    LIU, WT
    CHEN, SS
    CAVIN, R
    IEEE TRANSACTIONS ON SYSTEMS MAN AND CYBERNETICS, 1993, 23 (02): : 539 - 546
  • [3] A BIT-SERIAL ARCHITECTURE FOR DIGITAL SIGNAL-PROCESSING
    KANOPOULOS, N
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1985, 32 (03): : 289 - 291
  • [4] A field programmable bit-serial digital signal processor
    Rahim, SA
    Turner, LE
    4TH IEEE INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS, 2004, : 295 - 298
  • [5] A Compact FPGA Implementation of a Bit-Serial SIMD Cellular Processor Array
    Walsh, Declan
    Dudek, Piotr
    2012 13TH INTERNATIONAL WORKSHOP ON CELLULAR NANOSCALE NETWORKS AND THEIR APPLICATIONS (CNNA), 2012,
  • [6] SIMDRAM: A Framework for Bit-Serial SIMD Processing using DRAM
    Hajinazar, Nastaran
    Oliveira, Geraldo F.
    Gregorio, Sven
    Ferreira, Joao Dinis
    Ghiasi, Nika Mansouri
    Patel, Minesh
    Alser, Mohammed
    Ghose, Saugata
    Gomez-Luna, Juan
    Mutlu, Onur
    ASPLOS XXVI: TWENTY-SIXTH INTERNATIONAL CONFERENCE ON ARCHITECTURAL SUPPORT FOR PROGRAMMING LANGUAGES AND OPERATING SYSTEMS, 2021, : 329 - 345
  • [7] Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs
    Takamaeda-Yamazaki, Shinya
    Nakatsuka, Hiroshi
    Tanaka, Yuichiro
    Kise, Kenji
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2015, E98D (12): : 2150 - 2158
  • [8] A CMOS Imager With a Programmable Bit-Serial Column-Parallel SIMD/MIMD Processor
    Yamashita, Hirofumi
    Sodini, Charles G.
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2009, 56 (11) : 2534 - 2545
  • [9] High speed bit-serial parallel processing on array architecture
    Ito, K
    Shimizugashira, T
    Kunieda, H
    PROCEEDINGS OF THE ASP-DAC '97 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1997, 1996, : 667 - 668
  • [10] A CMOS DESIGN STRATEGY FOR BIT-SERIAL SIGNAL-PROCESSING
    MURRAY, AF
    DENYER, PB
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1985, 20 (03) : 746 - 753