A comparison of bit-serial and multi-bit processor elements in a real-time signal processing SIMD architecture

被引：0
|
作者：
Astrom, A
Hall, M
Edman, A
机构：
来源：
3RD INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING, PROCEEDINGS | 1996年
关键词：
D O I：
10.1109/HIPC.1996.565830
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
Today, it is accepted to say that the more bits you have got in your micro processor, the better performance you will have. This is probably true if only the performance is concerned. However, if the chip size of the processor is taken into account this might not be the case. In massively parallel architecture, chip area is an important figure. This is especially true for air-borne and, to certain extend industrial real-time applications. In this paper we study the impact of multi bit processors on the linear SIMD array called RVIP which is an architecture used for real-time radar signal processing. In RVIP, each processing element is bit serial. The results show that the gain in using multi bit processors is very little and that the optimal bit number probably is one or two. We believe that the results from this study can be transferred to other similar systems.
引用
收藏
页码：245 / 250
页数：6
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