共 50 条
- [41] Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling Journal of Electronic Testing: Theory and Applications (JETTA), 1991, 2 (04): : 351 - 372
- [42] Software-Hardware-Cooperated Built-In Self-Test Scheme for Channel-Based DRAMs 2017 INTERNATIONAL TEST CONFERENCE IN ASIA (ITC-ASIA), 2017, : 107 - 111
- [43] Stimulus generation for built-in self-test of charge-pump phase-locked loops INTERNATIONAL TEST CONFERENCE 1998, PROCEEDINGS, 1998, : 698 - 707
- [45] An Improved Pattern Generation for Built-in Self-test Design Based on Boundary-scan Reseeding 2009 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLUMES I & II: COMMUNICATIONS, NETWORKS AND SIGNAL PROCESSING, VOL I/ELECTRONIC DEVICES, CIRUITS AND SYSTEMS, VOL II, 2009, : 1082 - +
- [47] A Power Detector for Built-In Self-Test of 4-Channel Beamforming Transceiver in Phased Array Systems 2022 IEEE INTERNATIONAL SYMPOSIUM ON PHASED ARRAY SYSTEMS & TECHNOLOGY (PAST), 2022,
- [48] Built-in test with modified-booth high-speed pipelined multipliers and dividers JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2003, 19 (03): : 245 - 269
- [49] Design of Clock Generation Circuitry for High-Speed Subranging Time-Interleaved ADCs 2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2017, : 2408 - 2411
- [50] Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers Journal of Electronic Testing, 2003, 19 : 245 - 269