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- [2] A BUILT-IN SELF-TEST STRUCTURE FOR ARITHMETIC EXECUTION UNITS OF VLSIS ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS, 1995, 78 (04): : 68 - 78
- [3] Synthesis for arithmetic built-in self-test Proceedings of the IEEE VLSI Test Symposium, 2000, : 165 - 170
- [5] Arithmetic pattern generators for built-in self-test INTERNATIONAL CONFERENCE ON COMPUTER DESIGN - VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1996, : 131 - 134
- [6] Design for testability and built-in self-test of mixed-signal circuits: A tutorial TENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1997, : 388 - 392
- [10] Arithmetic test and design-for-testability for FFT processor Yi Qi Yi Biao Xue Bao/Chinese Journal of Scientific Instrument, 2007, 28 (04): : 657 - 662