Stimulus generation for built-in self-test of charge-pump phase-locked loops

被引:12
|
作者
Veillette, BR [1 ]
Roberts, GW [1 ]
机构
[1] McGill Univ, Microelect & Comp Syst Lab, Montreal, PQ H3A 2A7, Canada
来源
INTERNATIONAL TEST CONFERENCE 1998, PROCEEDINGS | 1998年
关键词
D O I
10.1109/TEST.1998.743214
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper addresses the issue of the stimulation of charge-pump phase-locked loops for built-in self-test applications. It is shown that three nodes of the PLL qualify for test signal injection. The hardware and methodology for each are discussed. In particular, a comprehensive explanation of the use of delta-sigma modulation in the time domain is provided. Furthermore, implementation issues of analog tests with signal generation based on coarse quantization are discussed. The effects of the quantization noise arising from delta-sigma modulation on the dynamic range of phase-locked loop nodes is evaluated. Original experimental results validate one of the method which was not verified previously. In conclusion, the strengths and weakness of each of the three methods for phase-locked loop stimulation are highlighted.
引用
收藏
页码:698 / 707
页数:10
相关论文
共 50 条
  • [1] An All-Digital Built-In Self-Test for Charge-Pump Phase-Locked Loops
    Xia, Lanhua
    Wu, Jianhui
    Zhang, Meng
    2013 IEEE 8TH INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING (WISP), 2013, : 97 - 102
  • [2] All-digital built-in self-test scheme for charge-pump phase-locked loops
    Xia, Lanhua
    Tang, Jifei
    IET CIRCUITS DEVICES & SYSTEMS, 2021, 15 (01) : 1 - 10
  • [3] Built-in self-test structure for fault detection of charge-pump phase-locked loop
    Xia, Lanhua
    Wu, Jianhui
    Huang, Cheng
    Zhang, Meng
    IET CIRCUITS DEVICES & SYSTEMS, 2016, 10 (04) : 317 - 321
  • [4] Built-in self-test for phase-locked loops
    Hsu, CL
    Lai, YT
    Wang, SW
    IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2005, 54 (03) : 996 - 1002
  • [5] Built-in Self-Test Circuits for All-digital Phase-Locked Loops
    Chung, Ching-Che
    Chu, Wei-Jung
    Tsai, Yi-Ting
    2019 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS - TAIWAN (ICCE-TW), 2019,
  • [6] An analysis of charge-pump phase-locked loops
    Wang, ZD
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2005, 52 (10) : 2128 - 2138
  • [7] Analysis of charge-pump phase-locked loops
    Hanumolu, PK
    Brownlee, M
    Mayaram, K
    Moon, UK
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2004, 51 (09) : 1665 - 1674
  • [8] On the Stability of Charge-Pump Phase-Locked Loops
    Homayoun, Aliakbar
    Razavi, Behzad
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2016, 63 (06) : 741 - 750
  • [9] A methodology for systematic built-in self-test of phase-locked loops targeting at parametric failures
    Yu, Guo
    Li, Peng
    2007 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, 2007, : 432 - 441
  • [10] An all-digital built-in self-test for high-speed phase-locked loops
    Kim, SW
    Soma, M
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2001, 48 (02) : 141 - 150