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- [22] Test sequencing strategy with imperfect test ICEMI 2007: PROCEEDINGS OF 2007 8TH INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS, VOL I, 2007, : 744 - 747
- [24] Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage 2013 26TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2013 12TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID), 2013, : 273 - 278
- [25] Test-time Reduction Methodology: Innovative Ways to Reduce Test Time for Server Products PROCEEDINGS OF THE 2013 IEEE 15TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC 2013), 2013, : 718 - 722
- [26] Simultaneous Reduction in Test Data Volume and Test Time for TRC-Reseeding GLSVLSI'07: PROCEEDINGS OF THE 2007 ACM GREAT LAKES SYMPOSIUM ON VLSI, 2007, : 49 - 54
- [27] Balancing Test Cost Reduction vs. Measurements Accuracy at Test Time 2015 IEEE 13TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 2015,
- [29] A Test-Application-Count Based Learning Technique for Test Time Reduction 2015 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2015,
- [30] A Systematic Approach to Memory Test Time Reduction IEEE DESIGN & TEST OF COMPUTERS, 2008, 25 (06): : 560 - 570