A 0.8-MU-M CMOS TECHNOLOGY FOR HIGH-PERFORMANCE ASIC MEMORY AND CHANNELLESS GATE ARRAY

被引：0
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作者：
LIOU, FT
HAN, YP
BRYANT, FR
ZAMANIAN, M
机构：
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1989年 / 24卷 / 02期
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D O I：
10.1109/4.18598
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
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页码：380 / 387
页数：8
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