共 50 条
- [2] A MASTER CHIP DESIGN OF 0.5-MU MIXED BICMOS CMOS CHANNELLESS GATE ARRAY FAMILY IEICE TRANSACTIONS ON COMMUNICATIONS ELECTRONICS INFORMATION AND SYSTEMS, 1991, 74 (11): : 3749 - 3756
- [6] A 350 PS 50K 0.8 MU-M BICMOS GATE ARRAY WITH SHARED BIPOLAR CELL STRUCTURE PROCEEDINGS OF THE IEEE 1989 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1989, : 181 - 184
- [9] A SUPPLY VOLTAGE DESIGN FOR HALF MU-M BICMOS GATES 1989 SYMPOSIUM ON VLSI TECHNOLOGY: DIGEST OF TECHNICAL PAPERS, 1989, : 55 - 56