A 0.5 MU-M BICMOS CHANNELLESS GATE ARRAY

被引:0
|
作者
MURABAYASHI, F
NISHIO, Y
MAEJIMA, H
WATANABE, A
SHUKURI, S
NISHIDA, T
SHIMOHIGASHI, K
机构
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:189 / 192
页数:4
相关论文
共 50 条
  • [1] 0.5 MU-M CMOS GATE ARRAY WITH CROSSCHECK
    NAKAJIMA, K
    OHUCHI, K
    WATANABE, T
    TAKAGI, N
    KONDOU, K
    NEC RESEARCH & DEVELOPMENT, 1993, 34 (03): : 320 - 328
  • [2] A MASTER CHIP DESIGN OF 0.5-MU MIXED BICMOS CMOS CHANNELLESS GATE ARRAY FAMILY
    NISHIO, Y
    OKA, N
    TAKAHASHI, S
    SHIBATA, M
    IEICE TRANSACTIONS ON COMMUNICATIONS ELECTRONICS INFORMATION AND SYSTEMS, 1991, 74 (11): : 3749 - 3756
  • [3] 0.5-MU-M 2M-TRANSISTOR BIPNMOS CHANNELLESS GATE ARRAY
    HARA, H
    SAKURAI, T
    NODA, M
    NAGAMATSU, T
    SETA, K
    MOMOSE, H
    NIITSU, Y
    MIYAKAWA, H
    WATANABE, Y
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1991, 26 (11) : 1615 - 1620
  • [4] A 150K CHANNELLESS GATE ARRAY DESIGN IN 0.5-MU-M CMOS TECHNOLOGY
    ANDERSON, FE
    FORD, JM
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (02) : 520 - 522
  • [5] DESIGN OF THE BASIC CELL AND METALLIZED RAM FOR 0.5 MU-M CMOS GATE ARRAY
    NISHIO, Y
    HARA, H
    IWAMURA, M
    KAMINAGA, Y
    KOIKE, K
    HIROSE, K
    NOTO, T
    OGUCHI, S
    YAMAMOTO, Y
    ONO, T
    IEICE TRANSACTIONS ON ELECTRONICS, 1995, E78C (09) : 1255 - 1262
  • [6] A 350 PS 50K 0.8 MU-M BICMOS GATE ARRAY WITH SHARED BIPOLAR CELL STRUCTURE
    HARA, H
    SUGIMOTO, Y
    NODA, M
    NAGAMATSU, T
    WATANABE, Y
    IWAI, H
    NIITSU, Y
    SASAKI, G
    MAEGUCHI, K
    PROCEEDINGS OF THE IEEE 1989 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1989, : 181 - 184
  • [7] A 0.8-MU-M CMOS TECHNOLOGY FOR HIGH-PERFORMANCE ASIC MEMORY AND CHANNELLESS GATE ARRAY
    LIOU, FT
    HAN, YP
    BRYANT, FR
    ZAMANIAN, M
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (02) : 380 - 387
  • [9] A SUPPLY VOLTAGE DESIGN FOR HALF MU-M BICMOS GATES
    MOMOSE, H
    UNNO, Y
    MAEDA, T
    1989 SYMPOSIUM ON VLSI TECHNOLOGY: DIGEST OF TECHNICAL PAPERS, 1989, : 55 - 56
  • [10] IMPROVED ARRAY ARCHITECTURES OF DINOR FOR 0.5 MU-M 32 M AND 64 MBIT FLASH MEMORIES
    ONODA, H
    KUNORI, Y
    YUZURIHA, K
    KOBAYASHI, S
    SAKAKIBARA, K
    OHI, M
    FUKUMOTO, A
    AJIKA, N
    HATANAKA, M
    MIYOSHI, H
    IEICE TRANSACTIONS ON ELECTRONICS, 1994, E77C (08) : 1279 - 1286