ANALYZING MULTIPLE FAULTS IN SYNCHRONOUS SEQUENTIAL-CIRCUITS BY BOOLEAN DIFFERENCE TECHNIQUES

被引:0
|
作者
DAS, SR
NAYAK, AR
NGUYEN, T
机构
[1] Department of Electrical Engineering, University of Ottawa, Ottawa, ON
[2] Department of Systems and Computer Engineering, Carleton University, Ottawa, ON
[3] Department of Electrical Engineering, University of Ottawa, Ottawa, ON
关键词
D O I
10.1080/01969729008902253
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The Boolean difference is a mathematical concept that has proved its usefulness in the study of single and multiple “stuck-at" faults in combinational circuits. Goldstein has extended his tool of analysis to cover the multiple stuck-at faults Asynchronous sequential circuits. In this paper, modifications to Goldstein's paper are presented, together with a new method for deriving the required shortest test sequence to detect a specified multiple fault. © 1990 Taylor & Francis Group, LLC.
引用
收藏
页码:461 / 474
页数:14
相关论文
共 50 条
  • [41] On masking of redundant faults in synchronous sequential circuits with design-for-testability logic
    Pomeranz, I
    Reddy, SM
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2005, 24 (02) : 288 - 294
  • [42] Boolean Difference Technique for Detecting All Missing Gate Faults in Reversible Circuits.
    Mondal, Joyati
    Mondal, Bappaditya
    Kole, Dipak
    Rahaman, Hafizur
    KDas, Debesh
    2015 IEEE 18TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS 2015), 2015, : 95 - 98
  • [43] On generating tests that avoid the detection of redundant faults in synchronous sequential circuits with full scan
    Pomeranz, I
    Reddy, SM
    IEEE TRANSACTIONS ON COMPUTERS, 2006, 55 (04) : 491 - 495
  • [44] Boolean Difference Technique for Detecting All Missing Gate and Stuck-at Faults in Reversible Circuits
    Mondal, Joyati
    Mondal, Bappaditya
    Kole, Dipak Kumar
    Rahaman, Hafizur
    Das, Debesh Kumar
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2019, 28 (12)
  • [45] On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits
    Keller, KJ
    Takahashi, H
    Saluja, KK
    Takamatsu, Y
    INTERNATIONAL TEST CONFERENCE 2001, PROCEEDINGS, 2001, : 568 - 577
  • [46] On application of output masking to undetectable faults in synchronous sequential circuits with design-for-testability logic
    Pomeranz, I
    Reddy, SM
    ICCAD-2003: IEEE/ACM DIGEST OF TECHNICAL PAPERS, 2003, : 867 - 872
  • [47] Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits
    Pomeranz, Irith
    Reddy, Sudhakar M.
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2009, 28 (03) : 426 - 432
  • [48] Double-single stuck-at faults: A delay fault model for synchronous sequential circuits
    School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, United States
    不详
    IEEE Trans Comput Aided Des Integr Circuits Syst, 2009, 1 (426-432):
  • [49] Dynamic test compaction for synchronous sequential circuits using static compaction techniques
    Pomeranz, I
    Reddy, SM
    PROCEEDINGS OF THE TWENTY-SIXTH INTERNATIONAL SYMPOSIUM ON FAULT-TOLERANT COMPUTING, 1996, : 53 - 61
  • [50] Pseudo-exhaustive Testing of Sequential Circuits for Multiple Stuck-at Faults
    Matrosova, A.
    Mitrofanov, E.
    PROCEEDINGS OF 2016 IEEE EAST-WEST DESIGN & TEST SYMPOSIUM (EWDTS), 2016,