GRAPHICS ASIC DESIGN USING VHDL

The design of graphics ASICs for geometry and rasterisation processing has traditionally involved the use of schematic design entry whereby functional blocks are netlisted and instantiated on the schematic. This methodology is fine at the top most hierarchical levels of a design but becomes tedious and error prone at the lower gate levels. Often these designs are targeted at custom ASICs through the use of silicon compiler technology. Unfortunately, this is an expensive and risky approach to implementing these ASICs, particularly for University research laboratories where additional funding may not be available to cover non-recurring engineering costs, such as multiple mask runs, which may be needed due to design errors. This paper presents an alternative to these traditional approaches. A new approach, top down ASIC design with logic synthesis and optimisation targeting FPGA ASICs, is presented. Furthermore, exciting new reconfigurable FPGA, FPIC, and MCM technologies are now becoming available at a fraction of the cost of ASIC fabrication. These are ideal for prototyping, and we can reuse this technology for many new graphics hardware designs. We demonstrate through some examples of our graphics rasterisation hardware the benefits of this new approach.