ANALYSIS OF THE HOLDING CURRENT IN CMOS LATCH-UP

被引：1
|
作者：
MATINO, H
机构：
来源：
IBM JOURNAL OF RESEARCH AND DEVELOPMENT | 1985年 / 29卷 / 06期
关键词：
SEMICONDUCTOR DEVICES; MOS;
D O I：
10.1147/rd.296.0588
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The holding current in CMOS latch-up with or without well and/or substrate bias has been examined. Measurements indicate that the holding current increases significantly with reverse bias and low shunting base resistance. It is shown that a previous equation for the holding current is inaccurate, and a new equation for holding current with bias is presented.
引用
收藏
页码：588 / 592
页数：5
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