Improvement of CMOS Latch-Up in Bootstrapping Circuit Application

被引：0

作者：

Tsai, Jung-Ruey ^{[1
]}

Chang, Yi-Sheng ^{[1
]}

Lin, Jui-Chang ^{[1
]}

Bai, Shu-Ming ^{[2
]}

Sheu, Gene ^{[1
,2
]}

Yang, Shao-Ming ^{[2
]}

Wu, Chun-Hsien ^{[1
]}

机构：

[1] Asia Univ, Dept Photon & Commun Engn, Taichung 41354, Taiwan

[2] Asia Univ, Dept Comp Sci & Informat Engn, Taichung 41354, Taiwan

来源：

2014 INTERNATIONAL SYMPOSIUM ON NEXT-GENERATION ELECTRONICS (ISNE) | 2014年

关键词：

CMOS; latch-up; booststrapping;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work presents a design guideline for free latch-up in the CMOS inverter caused by shifting time waveform for various device sizes which is demonstrated by 2D TCAD simulations. The design window for improving the CMOS latch-up is investigated by increasing distance anode to cathode of parasitic silicon-controlled-rectifier (SCR) or source to bulk of NMOS.

引用

页数：3

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