A TRANSIENT ANALYSIS OF LATCHUP IN BULK CMOS

被引：52
|
作者：
TROUTMAN, RR
ZAPPE, HP
机构：
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 1983年 / 30卷 / 02期
关键词：
D O I：
10.1109/T-ED.1983.21091
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：170 / 179
页数：10
相关论文
共 50 条
  • [21] An Experimental Extracted Model for Latchup Analysis in CMOS Process
    Li, Ye
    Gong, Xiaohan
    Xu, Weiwei
    Hong, Zhiliang
    Killat, Dirk
    2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2009, : 1035 - +
  • [22] Transient-induced latchup in CMOS technology: Physical mechanism and device simulation
    Ker, MD
    Hsu, SF
    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, : 937 - 940
  • [23] Transient-induced latchup in CMOS integrated circuits due to electrical fast transient (EFT) test
    Yen, Cheng-Cheng
    Ker, Ming-Dou
    IPFA 2007: PROCEEDINGS OF THE 14TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS, 2007, : 253 - +
  • [24] Impact of Deep P-Well Structure on Single Event Latchup in Bulk CMOS
    Kato, Takashi
    Matsuyama, Hideya
    2015 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD), 2015, : 365 - 368
  • [25] LATCHUP MODEL FOR THE PARASITIC P-N-P-N PATH IN BULK CMOS
    FANG, RCY
    MOLL, JL
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1984, 31 (01) : 113 - 120
  • [26] PARAMETRIC STUDY OF LATCHUP IMMUNITY OF DEEP TRENCH-ISOLATED, BULK, NONEPITAXIAL CMOS
    BHATTACHARYA, S
    BANERJEE, SK
    LEE, JC
    TASCH, AF
    CHATTERJEE, A
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1992, 39 (04) : 921 - 931
  • [27] Preventing latchup in CMOS DACs
    Alexander, Mark
    Powerconversion and Intelligent Motion, 1988, 14 (11): : 54 - 59
  • [28] LAYOUT DEPENDENCE OF CMOS LATCHUP
    MENOZZI, R
    SELMI, L
    SANGIORGI, E
    CRISENZA, G
    CAVIONI, T
    RICCO, B
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1988, 35 (11) : 1892 - 1901
  • [29] QUASI-2-DIMENSIONAL SIMULATION OF TRANSIENT LATCHUP EFFECT IN VLSI CMOS CIRCUITS
    HARTER, J
    JACOBS, H
    ZWAR, M
    SKAPA, H
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (09) : 1665 - 1668
  • [30] AN EFFICIENT TWO-DIMENSIONAL MODEL FOR CMOS LATCHUP ANALYSIS
    CHEN, MJ
    WU, CY
    SOLID-STATE ELECTRONICS, 1986, 29 (04) : 395 - 407
12345