A PRACTICAL CURRENT SENSING TECHNIQUE FOR I-DDQ TESTING

被引:34
|
作者
TANG, JJ
LEE, KJ
LIU, BD
机构
[1] Department of Electrical Engineering, National Cheng-Kung University, Tainan
关键词
D O I
10.1109/92.386229
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, a practical design for built-in current sensors (BICS's) is proposed. This scheme can execute current testing during the normal circuit operation with very small impact on the performance of the circuit under test (CUT). In addition, scalable resolutions and no external voltage/current reference make this design more effective and efficient than previous designs. Moreover this scheme can be used to monitor the current-related faults of both CMOS and non-CMOS circuits. Thus it is highly suitable for design for testability (DFT) on a multiple-chip module (MCM) or to be the current monitor on the test fixture under the quality test action group (QTAG) standard [1].
引用
收藏
页码:302 / 310
页数:9
相关论文
共 50 条
  • [31] I-DDQ TEST AND DIAGNOSIS OF CMOS CIRCUITS
    ISERN, E
    FIGUERAS, J
    IEEE DESIGN & TEST OF COMPUTERS, 1995, 12 (04): : 60 - 67
  • [32] TEST-GENERATION FOR I-DDQ TESTING OF BRIDGING FAULTS IN CMOS CIRCUITS
    BOLLINGER, SW
    MIDKIFF, SF
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1994, 13 (11) : 1413 - 1418
  • [33] Correlating defects to functional and I-DDQ tests
    Powell, TJ
    Pair, JR
    Carbajal, BG
    INTERNATIONAL TEST CONFERENCE 1996, PROCEEDINGS, 1996, : 501 - 510
  • [34] ITA: An algorithm for I-DDQ testability analysis
    McNamer, MG
    Nagle, HT
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1996, 8 (03): : 287 - 298
  • [35] Some faults need an I-ddq test
    Makar, SR
    McCluskey, EJ
    1996 IEEE INTERNATIONAL WORKSHOP ON IDDQ TESTING, DIGEST OF PAPERS, 1996, : 102 - 103
  • [36] I-DDQ test invalidation by break faults
    Dalpasso, M
    Favalli, M
    Olivo, P
    ELECTRONICS LETTERS, 1996, 32 (11) : 994 - 995
  • [37] Optical emission diagnostics for excess I-DDQ
    Kash, JA
    Tsang, JC
    Rizzolo, RF
    Patel, AK
    Shore, AD
    PROCEEDINGS OF THE IEEE 1997 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1997, : 23 - 26
  • [38] Separate I-DDQ testing of signal and bias paths in CMOS ICs for defect diagnosis
    Sachdev, M
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1996, 8 (02): : 203 - 214
  • [39] I-DDQ detectable bridges in combinational CMOS circuits
    Isern, E
    Figueras, J
    VLSI DESIGN, 1997, 5 (03) : 241 - 252
  • [40] I-DDQ TEST AS A VLSI FAILURE ANALYSIS TOOL
    SYLVESTRI, J
    OUIMET, P
    EE-EVALUATION ENGINEERING, 1995, 34 (05): : 36 - 40