Review of FinFET Devices and Perspective on Circuit Design Challenges

In recent technology, the demand for 3D multiple-gate MOSFETs such as FinFETs increase. In this paper, FinFETs are explored and reviewed. The scaling of planar MOSFET below 32nm technology increases the short channel effects (SCE). To improve the concert in low-power VLSI logic circuits and reduced the SCEs, we need enhanced gate controlling over the channel by using multigate technology. Here, we have discussed numerous architecture of FINFET, the threshold voltage (Vth) and supply voltage (Vdd) optimization, optimization of fin configuration, and low power technique for FinFET domino circuits.