Impact of gate-on-source misalignment on the analog and digital performance of tunnel FET

The tunnel FET (TFET) is considered a promising candidate which can be used in the design of digital and analog circuits in low-power applications. Due to fabrication tolerances, it is not guaranteed that the gate electrode is perfectly aligned on the channel, especially for short channel structures. In this work, we investigate the effect of gate misalignment towards the source by using TCAD simulations. The proposed structure is presented in which a low-k dielectric pocket is inserted above the source and beneath the high-k gate oxide to mitigate the undesirable impact of gate misalignment. We show that the insertion of a silicon dioxide (SiO2)\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$_{{2}})$$\end{document} pocket above the source enhances the DC performance (in terms of ON/OFF ratio, threshold voltage and subthreshold swing (SS)), RF performance (in terms of cut-off frequency) and it also improves the transient response of the inverter circuits.