A low cost network-on-chip with guaranteed service well suited to the GALS approach

被引：0
|
作者：
Panades, Ivan Miro
Greiner, Alain
Sheibanyrad, Abbas
机构：
[1] STMicroelectronics, F-38054 Grenoble, France
[2] UPMC, F-75252 Paris, France
来源：
2006 1ST INTERNATIONAL CONFERENCE ON NANO-NETWORKS AND WORKSHOPS | 2006年
关键词：
DSPIN; SPIN; network on chip; NoC; system on chip; SoC; globally asynchronous locally synchronous; GALS; mesochronous; Bi-synchronous FIFO;
D O I：
暂无
中图分类号：
TB3 [工程材料学];
学科分类号：
0805 ; 080502 ;
摘要：
The paper presents the DSPIN micro-network, that is an evolution of the SPIN architecture. DSPIN is a scalable packet switching micro-network dedicated to GALS (Globally Asynchronous, Locally Synchronous) clustered, multi-processors, systems on chip. The DSPIN architecture has a very small footprint and provides to the system designer both guaranteed latency, and guaranteed throughput services for real-time applications.
引用
收藏
页码：34 / 38
页数：5
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