Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology

被引：2

作者：

Alvarez, David ^{[1
]}

Chatty, Kiran ^{[2
]}

Russ, Christian ^{[1
]}

Abou-Khalil, Michel J. ^{[2
]}

Li, Junjun ^{[2
]}

Gauthier, Robert ^{[2
]}

Esmark, Kai ^{[1
]}

Halbach, Ralph ^{[2
]}

Seguin, Christopher ^{[2
]}

机构：

[1] Infineon Technol, D-85579 Am Campeon, Neubiberg, Germany

[2] IBM Corp, Semicond Res Ctr, Essex Jct, VT 05452 USA

来源：

MICROELECTRONICS RELIABILITY | 2009年 / 49卷 / 12期

关键词：

D O I：

10.1016/j.microrel.2009.06.051

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Decrease of the drain silicide-blocking-to-gate spacing in gate-silicided-ESD-NMOSFETs improves the TLP and HBM failure levels up to 30%, while no effect is observed when decreasing the source silicide-blocking-to-gate spacing. Failure analysis and simulation results show that current crowding in the drain silicide region accounts for the difference in failure current for the devices. (C) 2009 Elsevier Ltd. All rights reserved.

引用

页码：1417 / 1423

页数：7

共 50 条

[21] 45-nm gate length CMOS technology and beyond using steep halo
Wakabayashi, H
Ueki, M
Narihiro, M
Fukai, T
Ikezawa, N
Matsuda, T
Yoshida, K
Takeuchi, K
Ochiai, Y
Mogami, T
Kunio, T
INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, : 49 - 52
[22] ESD nMOSFETs in Advanced Bulk FinFET Technology With Dual S/D Epitaxy
Chen, Wen-Chieh
Chen, Shih-Hung
Chiarella, Thomas
Hellings, Geert
Linten, Dimitri
Groeseneken, Guido
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2022, 69 (09) : 5357 - 5362
[23] Design and analysis of CMOS ring oscillator using 45 nm technology
Sikarwar, Vandna
Yadav, Neha
Akashe, Shyam
PROCEEDINGS OF THE 2013 3RD IEEE INTERNATIONAL ADVANCE COMPUTING CONFERENCE (IACC), 2013, : 1491 - 1495
[24] Degradation of High-k/Metal Gate nMOSFETs Under ESD-Like Stress in a 32-nm Technology
Yang, Yang
Gauthier, Robert J.
Chatty, Kiran
Li, Junjun
Mishra, Rahul
Mitra, Souvick
Ioannou, Dimitris E.
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2011, 11 (01) : 118 - 125
[25] Mismatch trends in 20nm Gate-last bulk CMOS technology
Rahhal, Lama
Bajolet, Aurelie
Manceau, Jean-Philippe
Rosa, Julien
Ricq, Stephane
Lassere, Sebastien
Ghibaudo, Gerard
2014 15TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (ULIS), 2014, : 133 - 136
[26] ESD design challenges in 28nm Hybrid FDSOI/Bulk advanced CMOS process
Dray, A.
Guitard, N.
Fonteneau, P.
Golanski, D.
Fenouillet-Beranger, C.
Beckrich, H.
Sithanandam, R.
Benoist, T.
Legrand, C-A.
Galy, Ph
2012 34TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD), 2012,
[27] Wafer Level Statistical Evaluation of the Proton Radiation Hardness of a High-κ Dielectric/Metal Gate 45 nm Bulk CMOS Technology
Claeys, C.
Iacovo, S.
Kobayashi, D.
Mercha, A.
Griffoni, A.
Roussel, Ph
Crupi, F.
Simoen, E.
HIGH PURITY SILICON 12, 2012, 50 (05): : 213 - 222
[28] ESD Characterization and Modeling of Cascoded, Silicided FETs in a 22nm FDSOI Technology
Loiseau, Alain
Yang, Xuejiao
Nath, Anindya
Mitra, Souvick
Forguites, John
Fortney, Michael
2020 42ND ANNUAL EOS/ESD SYMPOSIUM (EOS/ESD), 2020,
[29] Investigation of Ni fully silicided gates for sub-45 nm CMOS technologies
Pawlak, MA
Kittl, JA
Chamirian, O
Veloso, A
Lauwers, A
Schram, T
Maex, K
Vantomme, A
MICROELECTRONIC ENGINEERING, 2004, 76 (1-4) : 349 - 353
[30] A 45 nm gate length high performance SOI transistor for 100nm CMOS technology applications
Celik, M
Krishnan, S
Fuselier, M
Wei, A
Wu, D
En, B
Cave, N
Abramowitz, P
Min, B
Pelella, M
Yeh, P
Burbach, G
Taylor, B
Jeon, Y
Qi, WJ
Li, RG
Conner, J
Yeap, G
Woo, M
Mendicino, M
Karlsson, O
Wristers, D
2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2002, : 166 - 167

← 1 2 3 4 5 →