Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology

被引：2

作者：

Alvarez, David ^{[1
]}

Chatty, Kiran ^{[2
]}

Russ, Christian ^{[1
]}

Abou-Khalil, Michel J. ^{[2
]}

Li, Junjun ^{[2
]}

Gauthier, Robert ^{[2
]}

Esmark, Kai ^{[1
]}

Halbach, Ralph ^{[2
]}

Seguin, Christopher ^{[2
]}

机构：

[1] Infineon Technol, D-85579 Am Campeon, Neubiberg, Germany

[2] IBM Corp, Semicond Res Ctr, Essex Jct, VT 05452 USA

来源：

MICROELECTRONICS RELIABILITY | 2009年 / 49卷 / 12期

关键词：

D O I：

10.1016/j.microrel.2009.06.051

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Decrease of the drain silicide-blocking-to-gate spacing in gate-silicided-ESD-NMOSFETs improves the TLP and HBM failure levels up to 30%, while no effect is observed when decreasing the source silicide-blocking-to-gate spacing. Failure analysis and simulation results show that current crowding in the drain silicide region accounts for the difference in failure current for the devices. (C) 2009 Elsevier Ltd. All rights reserved.

引用

页码：1417 / 1423

页数：7

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