ESD Protection Using Grounded Gate, Gate Non-Silicided (GG-GNS) ESD NFETs in 45nm SOI Technology

被引：0

作者：

Mitra, Souvick ^{[1
]}

Gauthier, Robert ^{[1
]}

Li, Junjun ^{[1
]}

Abou-Khalil, Michel ^{[1
]}

Putnam, Chris S. ^{[1
]}

Halbach, Ralph ^{[1
]}

Seguin, Christopher ^{[1
]}

机构：

[1] IBM Microelect Semicond Res & Dev Ctr, Essex Jct, VT 05452 USA

来源：

ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS - 2008 | 2008年

关键词：

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

A non-self protection ESD scheme using grounded-gate, gate non-silicided (GG-GNS) drain/source silicide blocked (SBLK) ESD NFET offered in 45nm SOI CMOS technology is presented based on a comprehensive study using the high current pulse characteristics. The results show that with a minimum SBLK width over drain/source, GG-GNS NFET can handle similar to 3.4mA/mu m current.

引用

页码：312 / 316

页数：5

共 23 条

[1] Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology
Alvarez, David
Chatty, Kiran
Russ, Christian
Abou-Khalil, Michel J.
Li, Junjun
Gauthier, Robert
Esmark, Kai
Halbach, Ralph
Seguin, Christopher
MICROELECTRONICS RELIABILITY, 2009, 49 (12) : 1417 - 1423
[2] Maximizing ESD Design Window by Optimizing Gate Bias for Cascoded Drivers in 45nm and Beyond SOI Technologies
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Gauthier, Robert
Chang, Shunhua
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Seguin, Chris
ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS 2010, 2010,
[3] Analysis of 65 nm technology grounded-gate NMOS for on-chip ESD protection applications
Dong, S.
Du, X.
Han, Y.
Huo, M.
Cui, Q.
Huang, D.
ELECTRONICS LETTERS, 2008, 44 (19) : 1129 - 1130
[4] ESD Device Design Strategy for High Speed I/O in 45nm SOI Technology
Cao, Shuqing
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Beebe, Stephen G.
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[5] An ESD protection circuit for SOI technology using gate- and body-biased MOSFET's
Salman, A
Mitra, S
Ioannou, DE
Fechner, P
Liu, M
2002 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2002, : 45 - 46
[6] Field Effect Diode for Effective CDM ESD Protection in 45 nm SOI Technology
Cao, Shuqing
Beebe, Stephen G.
Salman, Akram A.
Pelella, Mario M.
Chun, Jung-Hoon
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[7] Analysis of failure mechanism on gate-silicided and gate-non-silicided, drain/source silicide-hlocked ESD NMOSFETs in a 65nm bulk CMOS technology
Li, Junjun
Alvarez, David
Chatty, Kiran
Abou-Khalil, Michel J.
Gauthier, Robert
Russ, Christian
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[8] A High Voltage Tolerant Supply Clamp for ESD Protection in a 45-nm SOI Technology
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2022 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2022,
[9] Capacitance Investigation of Diode and GGNMOS for ESD Protection of High Frequency Circuits in 45nm SOI CMOS Technologies
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ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS - 2008, 2008, : 228 - 234
[10] A High Voltage Tolerant Supply Clamp for ESD Protection in a 45-nm SOI Technology
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Rosenbaum, Elyse
Parthasarathy, Srivatsan
Zhou, Yuanzhong
Hajjar, Jean-Jacques
2022 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2022,

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