ESD Device Design Strategy for High Speed I/O in 45nm SOI Technology

被引：0
|
作者：
Cao, Shuqing [1 ]
Salman, Akram A. [2 ]
Beebe, Stephen G. [2 ]
Pelella, Mario M. [2 ]
Chun, Jung-Hoon [3 ]
Dutton, Robert W. [1 ]
机构：
[1] Stanford Univ, CIS Extens, Integrated Circuits Lab, Room 332, Stanford, CA 94305 USA
[2] Adv Micro Devices Inc, Sunnyvale, CA 94088 USA
[3] Sungkyunkwan Univ, Sch Informat & Commun Engn, Suwon, South Korea
来源：
ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS - 2008 | 2008年
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中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
This work focuses on characterization, modeling, and design of three different ESD protection devices for high-speed I/O applications in 45nm silicon-on-insulator (SOI) technology. In this paper, the gated diode, the bulk substrate diode, and a double-well field-effect diode are evaluated using very fast transmission line pulse (VF-TLP) test method.
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页码：235 / +
页数：3
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