Post-Silicon Validation in the SoC Era: A Tutorial Introduction

被引：38

作者：

Mishra, Prabhat ^{[1
,2
]}

Ray, Sandip ^{[7
]}

Morad, Ronny ^{[3
,4
]}

Ziv, Avi ^{[5
,6
]}

机构：

[1] Univ Florida, CISE Dept, Gainesville, FL 32611 USA

[2] Univ Calif Irvine, Irvine, CA USA

[3] IBM Res, Haifa lab, Post Silicon Validat Technol & Analyt Grp, Haifa, Israel

[4] Tel Aviv Univ, Tel Aviv, Israel

[5] IBM Res, Hardware Verificat Technol Dept, Haifa, Israel

[6] Stanford Univ, Stanford, CA 94305 USA

[7] Univ Texas Austin, Austin, TX 78712 USA

来源：

IEEE DESIGN & TEST | 2017年 / 34卷 / 03期

基金：

美国国家科学基金会;

关键词：

TRACE-SIGNAL SELECTION; STATE RESTORATION; GENERATION;

D O I：

10.1109/MDAT.2017.2691348

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Editor's note: Post-silicon validation is a complex and critical component of a modern system-on-chip (SoC) design verification. It includes a large number of inter-related activities each with its own nuance and subtleties, requires extensive planning, and spans the entire system design lifecycle. This article provides a comprehensive high-level overview of the various facets of post-silicon validation, and includes industrial case studies illustrating their real-life application. - Swarup Bhunia, University of Florida © 2013 IEEE.

引用

页码：68 / 92

页数：25

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