Post-Silicon Validation in the SoC Era: A Tutorial Introduction

被引：38

作者：

Mishra, Prabhat ^{[1
,2
]}

Ray, Sandip ^{[7
]}

Morad, Ronny ^{[3
,4
]}

Ziv, Avi ^{[5
,6
]}

机构：

[1] Univ Florida, CISE Dept, Gainesville, FL 32611 USA

[2] Univ Calif Irvine, Irvine, CA USA

[3] IBM Res, Haifa lab, Post Silicon Validat Technol & Analyt Grp, Haifa, Israel

[4] Tel Aviv Univ, Tel Aviv, Israel

[5] IBM Res, Hardware Verificat Technol Dept, Haifa, Israel

[6] Stanford Univ, Stanford, CA 94305 USA

[7] Univ Texas Austin, Austin, TX 78712 USA

来源：

IEEE DESIGN & TEST | 2017年 / 34卷 / 03期

基金：

美国国家科学基金会;

关键词：

TRACE-SIGNAL SELECTION; STATE RESTORATION; GENERATION;

D O I：

10.1109/MDAT.2017.2691348

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Editor's note: Post-silicon validation is a complex and critical component of a modern system-on-chip (SoC) design verification. It includes a large number of inter-related activities each with its own nuance and subtleties, requires extensive planning, and spans the entire system design lifecycle. This article provides a comprehensive high-level overview of the various facets of post-silicon validation, and includes industrial case studies illustrating their real-life application. - Swarup Bhunia, University of Florida © 2013 IEEE.

引用

页码：68 / 92

页数：25

共 50 条

[31] A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation
Adir, Allon
Copty, Shady
Landa, Shimon
Nahir, Amir
Shurek, Gil
Ziv, Avi
Meissner, Charles
Schumann, John
2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE), 2011, : 1590 - 1595
[32] Special Session 12B: Panel Post-Silicon Validation & Test in Huge Variance Era
Yamaguchi, Takahiro J.
Abraham, Jacob A.
Roberts, Gordon W.
Natarajan, Suriyaprakash
Ciplickas, Dennis
2013 IEEE 31ST VLSI TEST SYMPOSIUM (VTS), 2013,
[33] A Distributed AXI-based Platform for Post-Silicon Validation
Neishaburi, M. H.
Zilic, Zeljko
2011 IEEE 29TH VLSI TEST SYMPOSIUM (VTS), 2011, : 8 - 13
[34] Automation of Test Program Synthesis for Processor Post-silicon Validation
Vasudevan Madampu Suryasarman
Santosh Biswas
Aryabartta Sahu
Journal of Electronic Testing, 2018, 34 : 83 - 103
[35] Trace-based post-silicon validation for vlsi circuits
Liu, Xiao
Xu, Qiang
1600, Springer Verlag, Tiergartenstrasse 17, Heidelberg, D-69121, Germany (252): : 1 - 123
[36] Red Baron: Near/Post-Silicon SoC Cache Coherence Stress Tester
You, Junbok
Bural, David
Brown, Jim
Zbiciak, Joe
2016 IEEE DALLAS CIRCUITS AND SYSTEMS CONFERENCE (DCAS), 2016,
[37] Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs
Ko, Ho Fai
Kinsman, Adam B.
Nicolici, Nicola
2008 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, 2008, : 422 - 431
[38] Coverage Evaluation of Post-silicon Validation Tests with Virtual Prototypes
Cong, Kai
Lei, Li
Yang, Zhenkun
Xie, Fei
2014 DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION (DATE), 2014,
[39] Emulation Infrastructure for the Evaluation of Hardware Assertions for Post-Silicon Validation
Taatizadeh, Pouya
Nicolici, Nicola
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 25 (06) : 1866 - 1880
[40] Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks
Damljanovic, Aleksa
Jutman, Artur
Squillero, Giovanni
Tsertov, Anton
2019 IEEE EUROPEAN TEST SYMPOSIUM (ETS), 2019,

← 1 2 3 4 5 →