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- [2] Hierarchical Trigger Generation for Post-silicon Debugging 2011 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2011, : 378 - 381
- [4] On-Chip Stimuli Generation for Post-Silicon Validation 2012 IEEE INTERNATIONAL HIGH LEVEL DESIGN VALIDATION AND TEST WORKSHOP (HLDVT), 2012, : 108 - 109
- [7] Resource-Efficient Programmable Trigger Units for Post-Silicon Validation ETS 2009: EUROPEAN TEST SYMPOSIUM, PROCEEDINGS, 2009, : 17 - 22
- [9] Automatic Concolic Test Generation with Virtual Prototypes for Post-silicon Validation 2013 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2013, : 303 - 310
- [10] On Signal Tracing in Post-Silicon Validation 2010 15TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2010), 2010, : 259 - 264