共 50 条
- [1] Design And Implementation Of Binary And Quaternary Low Power Selective Circuit Using Single Electron Transistor 2015 INTERNATIONAL CONFERENCE ON CONTROL, INSTRUMENTATION, COMMUNICATION AND COMPUTATIONAL TECHNOLOGIES (ICCICCT), 2015, : 121 - 126
- [2] Design of Systolic Array Multiplier Circuit using Reversible Logic 2017 2ND IEEE INTERNATIONAL CONFERENCE ON RECENT TRENDS IN ELECTRONICS, INFORMATION & COMMUNICATION TECHNOLOGY (RTEICT), 2017, : 1670 - 1673
- [5] Design and Implementation of High Efficiency Vedic Binary Multiplier Circuit based on Squaring Circuits 2017 2ND IEEE INTERNATIONAL CONFERENCE ON RECENT TRENDS IN ELECTRONICS, INFORMATION & COMMUNICATION TECHNOLOGY (RTEICT), 2017, : 973 - 977
- [7] A low power multiplier using adiabatic charging binary decision diagram circuit JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2000, 39 (4B): : 2305 - 2311
- [8] Low power multiplier using adiabatic charging binary decision diagram circuit Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 2000, 39 (5 B): : 2305 - 2311
- [9] Power efficient circuit design ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 435 - 438
- [10] Implementation of Reversible Multiplier Circuit Using Deoxyribonucleic Acid 2013 IEEE 13TH INTERNATIONAL CONFERENCE ON BIOINFORMATICS AND BIOENGINEERING (BIBE), 2013,