A Power Efficient Binary Multiplier Circuit with Overflow Detection Using Single Spin Logic Circuit: Design and Implementation

被引:0
|
作者
Ghosh, Ankush [1 ]
Sarkar, Souvik [2 ]
Chaudhuri, D. Ray [3 ]
Sarkar, Subir Kumar [1 ]
机构
[1] Jadavpur Univ, Dept Elect & Telecommun Engn, Kolkata 700032, India
[2] Govt Coll Engn & Ceram Technol, Dept CSE, Kolkata 700015, India
[3] Univ Calcutta, Dept Elect Sci, Kolkata 700009, W Bengal, India
关键词
D O I
10.1166/asl.2009.1071
中图分类号
O [数理科学和化学]; P [天文学、地球科学]; Q [生物科学]; N [自然科学总论];
学科分类号
07 ; 0710 ; 09 ;
摘要
The basic needs of modern Electronic industry are low power consumption high operating speed and high integration density equipments. As a consequence, the search for new principle of operation of the small size and low power consuming devices is becoming more and more important. Recent advances in controlling quantum 'spin' effect have broaden the path for the newly emerging field, called 'spin based electronic' or 'spintronics.' It is not the electronic charge but the electrons spin that carry information and they offer opportunities for a new generation of novel devices that are extremely fast. In spin based electronics information is injected, stored or manipulated with spin degree of freedom. In the present work, several multipliers (with overflow detection capability) like unsigned array multipliers, unsigned tree multipliers and two's complement multipliers are realized employing single spin logic circuit to save area and time.
引用
收藏
页码:391 / 397
页数:7
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