Bit-Serial multiplier based Neural Processing Element with Approximate adder tree

被引:1
|
作者
Jo, Cheolwon [1 ]
Lee, KwangYeob [2 ]
机构
[1] Seokyeong Univ, Dept Elect & Comp Engn, Seoul, South Korea
[2] Seokyeong Univ, Dept Comp Engn, Seoul, South Korea
关键词
Deep Learning; Accelerator; MOA; LOA; low power;
D O I
10.1109/ISOCC50952.2020.9332993
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Deep learning algorithms are computationally intensive and require dedicated hardware accelerators. Deep learning algorithms repeat multiply-accumulate (MAC) operations. This process produces a large number of partial sums that account for about 60% of the total logic. Therefore, optimizing multi-operand adders (MOA) that add these partial sums can reduce the high resource utilization of deep learning accelerators. This study designed a neural processing element with approximate adders that reduces resource utilization without changing the accuracy of deep learning algorithms by using the fault tolerance property of deep learning algorithms. As a result, the accuracy dropped by only 0.04% with 4.7% less resource usage.
引用
收藏
页码:286 / 287
页数:2
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