Area and Power Efficient Multiplier-Less Architecture for FIR Differentiator

Digital FIR filters have been used for various signal processing tasks in embedded systems. This paper presents a novel architecture for implementation of an FIR differentiator in FPGA designed for a specific application. The designed component is to estimate the velocity from the suspension displacement in a semi-active suspension controller. The architectures of FIR are modified based on the direct and transposed form, with incremental changes in the manner in which the constant-coefficient multiplication is executed. The recoding of constant FIR filter coefficients using Canonic Signed Digit representation is explored. Three architectures are designed and compared for efficient usage of area of implementation in FPGA. It is observed that the architecture using CSD requires 16% lesser area, and the optimized architecture is an additional 5% more area-efficient and 16% lesser in complexity of design because of sharing of resources. An overall reduction in power consumption by 3% is observed and the computation of the FIR filter convolution sum is faster by 17%.