A shallow trench isolation for sub-0.13μm CMOS technologies

The design of a shallow trench isolation (STI) for sub-0.13 mu m CMOS technologies is described in this paper. The areas addressed and key results of the STI are as follows. (a) A deep UV lithography with a surface imaging resist can define trench openings down to 0.12 mu m with good linearity. (b) A new high density plasma (HDP) CVD oxide process is able to fill 0.16 mu m wide and 0.5 mu m deep trenches without voids and to maintain good junction leakage and charge to breakdown (Q(bd)). (c) Optimized Nwell/Pwell implant doses and well and channel stop (CS) implant energies are described using both experimental data and tuned device simulations. Interwell (N+-to-Nwell and P+-to-Pwell) isolation of 0.15 mu m or N+-to-P+ spacing of 0.3 mu m, and intrawell (N+-to-N+ and P+-to-P+) isolation of 0.12 mu m have been achieved. Latch-up is shown to correlate well with alpha(NPN) + alpha(PNP), the sum of the common base current gains of the parasitic NPN and PNP transistors. Good latch-up (holding voltage > 1.5V) has been achieved using 0.51 mu m deep trench with optimized CS and well implant conditions.