A New Electrothermally-Aware Methodology for Full-Chip Temperature Optimization

被引：0

作者：

Dong, Gang ^{[1
]}

Leng, Peng ^{[2
]}

Chai, Changchun ^{[2
]}

Yang, Yintang ^{[2
]}

机构：

[1] Xidian Univ, Inst Microelect, Xian 710071, Peoples R China

[2] Xidian Univ, Xian 710071, Peoples R China

来源：

2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2009年

基金：

中国国家自然科学基金;

关键词：

Electrothermal coupling; Temperature; Full chip; Optimization;

D O I：

10.1109/ASICON.2009.5351222

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Due to the fact that there is electrothermal coupling between power, delay, and temperature, the paper presents a new electrothermally-aware methodology for full-chip temperature optimization. The main idea is that characteristics of temperature distribution can be improved dramatically by a certain given delay penalty. As an example, based on HotSpot, the optimization for AMD Athlon 64 processor in 90-nm technology is given in the paper. Simulation results show that the chip temperature and power optimized by the proposed method are decreased, temperature gradient is also reduced(1).

引用

页码：1268 / +

页数：2

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