Two level compact simulation methodology for timing analysis of power-switched circuits

被引：0

作者：

Henzler, S

Georgakos, G

Berthold, J

Schmitt-Landsiedel, D

机构：

[1] Tech Univ Munich, D-80290 Munich, Germany

[2] Infineon Technol AG, Corp Log, D-81541 Munich, Germany

来源：

INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION | 2004年 / 3254卷

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Standby-power dissipation in ultra-deep submicron CMOS can be reduced by power switching. As the cut-off device has a strong impact on area consumption, minimum power-down time, signal delay and leakage suppression, a proper sizing of this device is of general importance. Therefore a two level compact simulation methodology is proposed which provides fast and accurate CAD support to the switch design task.

引用

页码：789 / 798

页数：10

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