Temperature-driven power and timing analysis for CMOS ULSI circuits

In this paper, we present a temperature-driven simulation framework for power and timing analysis of CMOS ULSI circuits. A Monte-Carlo based power and temperature iteration methodology is first employed for finding the nominal steady-state on-chip temperature profile. The temperature information and the input vectors used in power analysis are then utilized for temperature-dependent timing analysis. Simulation results show that the on-chip temperature gradient and temperature rise has great impact on circuit timing, and our tool provides important guidelines for thermally reliable ULSI circuit design and to enhance the overall chip performance.