Low power compact design of AFIA block cipher

被引：0

作者：

Park, Jinsub ^{[1
]}

Kim, Young-Dae ^{[1
]}

Yang, Sangwoon ^{[2
]}

You, Younggap ^{[1
]}

机构：

[1] Chungbuk Natl Univ, Sch Elect & Comp Engn, Cheongju, Chungbuk, South Korea

[2] Natl Secur Res Inst, Daejeon, South Korea

来源：

2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS | 2006年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a 32-bit hardware architecture reduced from the original 128-bit ARIA cryptographic algorithm. The hardware design in this paper is a low-power and compact version of ARIA for mobile environment. We use four S-boxes and modify a diffusion function and its data-path to reduce a hardware size. The proposed 32-bit ARIA needs 63 clock cycles to generate initial values for a round key and 356 clock cycles to encrypt a single message packet. The 32-bit ARIA has 13,893 gates. It is 62.5% smaller than the original 128-bit ARIA. The power consumption is 61.46mW, 9.71%, of the 128-bit version at 71 MHz.

引用

页码：313 / +

页数：2

共 50 条

[41] Security Analysis and Enhanced Design of a Dynamic Block Cipher
Zhao Guosheng
Wang Jian
CHINA COMMUNICATIONS, 2016, 13 (01) : 150 - 160
[42] Automated design of a lightweight block cipher with Genetic Programming
Polimon, Javier
Hernandez-Castro, Julio C.
Estevez-Tapiador, Juan M.
Ribagorda, Arturo
INTERNATIONAL JOURNAL OF KNOWLEDGE-BASED AND INTELLIGENT ENGINEERING SYSTEMS, 2008, 12 (01) : 3 - 14
[43] A Novel Block Cipher Design Paradigm for Secured Communication
Sparrow, R. D.
Adekunle, A. A.
Berry, R. J.
Farnish, R. J.
2016 ANNUAL IEEE SYSTEMS CONFERENCE (SYSCON), 2016, : 946 - 951
[44] Low-Data Cryptanalysis On SKINNY Block Cipher
Hua, Jialiang
Liu, Tai
Cui, Yulong
Qin, Lingyue
Dong, Xiaoyang
Cui, Huiyong
COMPUTER JOURNAL, 2023, 66 (04): : 970 - 986
[45] A reconfigurable and compact hardware architecture of CLEFIA block cipher with multi-configuration
Cheng, Xin
Zhu, Haowen
Xu, Yixuan
Zhang, Yongqiang
Xiao, Hao
Zhang, Zhang
MICROELECTRONICS JOURNAL, 2021, 114
[46] Low Power Implementation of Trivium Stream Cipher
Mora-Gutierrez, J. M.
Jimenez-Fernandez, C. J.
Valencia-Barrero, M.
INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2013, 7606 : 113 - 120
[47] Correlation Power Analysis on the PRESENT Block Cipher on an Embedded Device
Lo, Owen
Buchanan, William J.
Carson, Douglas
13TH INTERNATIONAL CONFERENCE ON AVAILABILITY, RELIABILITY AND SECURITY (ARES 2018), 2019,
[48] Power Attack and Protected Implementation on Lightweight Block Cipher SKINNY
Ge, Jing
Xu, Yifan
Liu, Ruiqian
Si, Enze
Shang, Ning
Wang, An
2018 13TH ASIA JOINT CONFERENCE ON INFORMATION SECURITY (ASIAJCIS 2018), 2018, : 69 - 74
[49] Technology-agnostic power optimization for AES block cipher
Chibani, Kais
Facon, Adrien
Guilley, Sylvain
Souissi, Youssef
2018 25TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2018, : 397 - 400
[50] Differential Power Attack on SM4 block cipher
Bai, Guoqiang
Fu, Hailiang
Li, Wei
Wu, Xingjun
2018 17TH IEEE INTERNATIONAL CONFERENCE ON TRUST, SECURITY AND PRIVACY IN COMPUTING AND COMMUNICATIONS (IEEE TRUSTCOM) / 12TH IEEE INTERNATIONAL CONFERENCE ON BIG DATA SCIENCE AND ENGINEERING (IEEE BIGDATASE), 2018, : 1494 - 1497

← 1 2 3 4 5 →