Low power compact design of AFIA block cipher

被引：0

作者：

Park, Jinsub ^{[1
]}

Kim, Young-Dae ^{[1
]}

Yang, Sangwoon ^{[2
]}

You, Younggap ^{[1
]}

机构：

[1] Chungbuk Natl Univ, Sch Elect & Comp Engn, Cheongju, Chungbuk, South Korea

[2] Natl Secur Res Inst, Daejeon, South Korea

来源：

2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS | 2006年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a 32-bit hardware architecture reduced from the original 128-bit ARIA cryptographic algorithm. The hardware design in this paper is a low-power and compact version of ARIA for mobile environment. We use four S-boxes and modify a diffusion function and its data-path to reduce a hardware size. The proposed 32-bit ARIA needs 63 clock cycles to generate initial values for a round key and 356 clock cycles to encrypt a single message packet. The 32-bit ARIA has 13,893 gates. It is 62.5% smaller than the original 128-bit ARIA. The power consumption is 61.46mW, 9.71%, of the 128-bit version at 71 MHz.

引用

页码：313 / +

页数：2

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