Design methodology for global resonant H-tree clock distribution networks

被引：7
|
作者：
Rosenfeld, Jonathan [1 ]
Friedman, Eby G. [1 ]
机构：
[1] Univ Rochester, Dept Elect & Comp Engn, 601 Elmwood Ave, Rochester, NY 14627 USA
来源：
2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS | 2006年
基金：
美国国家科学基金会;
关键词：
resonance; clock distribution networks; on-chip inductors and capacitors; H-tree sector;
D O I：
10.1109/ISCAS.2006.1693024
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two level resonant H-tree is presented, supporting the design of low power, low skew, and low jitter resonant H-tree clock distribution networks. Excellent agreement is shown between the proposed model and SpectraS simulations. A case study is presented that demonstrates the design of a two level resonant H-tree network, distributing a 5 GHz clock signal in a TSMC 0.18 mu m CMOS technology. The design methodology enables tradeoffs among design variables to be examined, such as the operating frequency, size of the on-chip inductors and capacitors, the output resistance of the driving buffer, and the interconnect width.
引用
收藏
页码：2073 / +
页数：2
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